In a network on a chip device, there is frequent need for a processing element to write data, then take actions (or instruct other processing elements to take action) upon that data. Due to the network on a chip architecture, however, delivery order of packets carrying the data and/or instructions for processing the data may not be guaranteed. Simply sending a packet with the data to be written, then sending a second packet to indicate that the data has been written is insufficient to ensure that the data has actually been written before the second packet arrives at a destination. If the packets arrive out of order at their respective destinations, a notification destination could be signaled that data has been written at a write destination before the data has actually arrived to be written at the write destination.
For this reason, once a processing element sent data to be written to a memory location, the processing element follows up by reading data from the written location to verify that the write has occurred. This is done both when configuring registers within a single network on a chip device and when writing registers in another network on a chip device.